Tutorial Microcontroller MCS-51 ATMEL ISP

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3. Timer/ Counter

 

The MCS-51 has two 16 bit Timer/ Counter register. Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters ( see figure 3.1. ).
In the Timer function, the register is incremented every mechine cycle.

Microcontroller Timer Counter

Figure 3.1. Diagram block Timer/ Counter Operation

As shown in figure 3.1., microcontroller can be used as timer or counter as you need. The question is, what you have to do, so the microcontroller will act as timer or counter. See left and right swicht on diagram blog. Microcontroller will act as timer when swicht position on upper and microcontroller will act as counter when swicht position on lower by controlling C/T bit on TMOD register. The right swicht position is depent on BIT GATE ( Register TMOD ), TR1 ( Register TCON ) dan INT1.


Timer/ Counter Mode Control ( TMOD ) Register

TIMER 1
TIMER 0
GATE
C/T
M1
M0
GATE
C/T
M1
M0

GATE
Gating control when set. Timer/ Counter X is enabled only while INTx pin is high and TRx control pin is set
C/T
Timer or Counter Selector cleared for Timer operation (input from internal system clock) and set for counter operation (input from Tx input pin)

 

M1
M0
Operating
0
0
8048 Timer, TLx serves as 5 bit prescaler
0
1
16 bit Timer/Counter THx and TLx are cascaded, there is no prescaler
1
0
8 bit auto reaload Timer/ Counter THx holds a value which is tobe reloaded into TLx each time it overflows
1
1
(Timer 0) TL0 is an 8 bit Timer/ Counter controlled by the standard timer 0 control bits
(Timer 1) Timer/ Counter 1 stopped

Timer/ Counter Control ( TCON ) Register

MSB
LSB
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0

 

BIT
SYMBOL
FUNCTION
TCON.7
TF1
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vector to interrupt routine, or clearing the bit in software.
TCON.6
TR1
Timer 1 Run control bit . Set/ cleared by software to turn Timer/ Counter on/off
TCON.5
TF0
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vector to interrupt routine, or clearing the bit in software.
TCON.4
TR0
Timer 1 Run control bit . Set/ cleared by software to turn Timer/ Counter on/off
TCON.3
IE1
Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed.
TCON.2
IT1
Interrupt 1 type control bit. Set/ cleared by software to specefy falling edge/ low level trigerred external interupts
TCON.1
IE0
Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed.
TCON.0
IT0
Interrupt 0 type control bit. Set/ cleared by software to specefy falling edge/ low level trigerred external interupts

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